Semiconductor memory devices include, for example, Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs), and Read Only Memories (ROMs). In general, a semiconductor memory device includes word lines, bit lines, and a sense amplifier. When a word line is selected and driven, a potential is generated on a corresponding bit line. A sense amplifier amplifies the potential. The time between when a word line is driven and when a potential is generated on a corresponding bit line and the time between when the potential is generated and when the sense amplifier amplifies the potential are very short and thus are substantially negligible. However, when the clock frequency of a semiconductor memory device is high, these times cannot be ignored. Especially, the difference between the following cases in the time between when a potential is generated and when a sense amplifier amplifies the potential is too large to ignore: a case where a word line far from the sense amplifier is driven and a case where a word line near the sense amplifier is driven. During the time between when a word line is driven and when a sense amplifier amplifies a potential, data is unstable. Thus, a soft error is prone to occur. A soft error is a phenomenon in which the logic of data is inverted due to radiation (for example, alpha radiation) incident from the outside.
Japanese Patent Application Publication No. 9-73782 discloses a semiconductor memory device including a plurality of timing adjustment circuits. Each of the timing adjustment circuits is provided for each cell array block. The timing adjustment circuit adjusts the respective operational timings of a sense amplifier, an input-side reset circuit, an output-side reset circuit, and an output circuit in the cell array block on the basis of clocks from a clock buffer. In the semiconductor memory device, the operational timings need not be readjusted every time the number of cell array blocks is increased. Moreover, in the semiconductor memory device, no margin needs to be prepared for the operational timings. Thus, the access speed is improved. However, in the semiconductor memory device disclosed in Patent Document 1, the timing of activation of a sense amplifier is not optimized in a manner that depends on a word line to be selected.
Japanese Patent Application Publication No. 2000-251472 discloses an integrated circuit having a programmable delay control function. The integrated circuit includes a plurality of arrays. Each of the arrays is partitioned into a plurality of blocks. Each of the blocks includes a block control circuit. Each block control circuit includes a sense amplifier, a sense amplifier control signal generation circuit, a delay adjustment circuit, and a secondary amplifier control signal generation circuit. The sense amplifier is coupled to local data lines, and the local data lines are coupled to a column decoder. The column decoder is coupled to memory cells via bit lines. The sense amplifier provides an output on global data lines. The integrated circuit further includes secondary amplifiers, delay adjustment circuits, and first and second fuse circuits. The block control circuit is coupled to the global data lines and provides an output to the corresponding secondary amplifier via the global data lines. Each of the delay adjustment circuits provides the timing of enabling the corresponding secondary amplifier. The amount of delay is determined on the basis of information provided from the second fuse circuit. The block control circuit provides a secondary amplifier control signal to the corresponding delay adjustment circuit. Triggering of the secondary amplifier by the delay adjustment circuit is initiated by a secondary amplifier delay signal delayed by an amount chosen by the second fuse circuit. The secondary amplifier may be turned on too early in case data provided on the global data lines is not sufficiently developed at the time the secondary amplifier is enabled. The delay adjustment circuit is located in close proximity to the secondary amplifier, and the block control circuit is located in close proximity to the corresponding block. Thus, a delay on the global data lines from the block to the secondary amplifier is matched to a delay on a line from the block control circuit to the delay adjustment circuit. Due to this matching, a signal development delay is very consistent between the delay adjustment circuit receiving the input and the secondary amplifier receiving data on the global data line. However, even in the integrated circuit disclosed in Patent Document 2, the timing of activation of a sense amplifier is not optimized in a manner that depends on a word line to be selected.